Articles

June 15,2021

How eNVM Helps Power Controllers Be Smarter

From smartphone to IoT, smart devices contain many different ICs that allow it to function the way it does. Within those ICs, PMIC helps deliver power from the battery to many semiconductor components.

PMIC designers have learned that using eNVMs like OTP in their chips can be very beneficial. A simple state machine with OTP can store power sequences and parameters, which can help manage the power between ICs efficiently.

ICs with special functions, such as envelope tracking, use OTP to store trimming information and provide accurate and dynamic power to better manage power consumption in RF systems. Another example is battery gauge IC, which is for monitoring battery status, can also use OTP to store trimming information or parameters like LUT to provide accurate battery level for users.

For smart power applications, such as wireless charging and USB power delivery, these power controllers usually require an embedded MCU to manage the power delivery behavior. Since MCU-based power controllers usually need the flexibility to update firmware, they require reliable multi-time programming capability

Traditional eFlash solutions are not ideal especially on BCD platforms since they require many additional masks to produce a memory block. This significantly raises the manufacturing cost, thus squeezing the product profit.

eMemory’s MTP is especially suitable for these MCU-based power controllers due to its zero-mask-adder design and reliable characteristics. Compared to eFlash, eMemory’s floating-gate technology MTP provides good improves performance in terms of endurance, reliability, read/write speed, and, especially when considering the cost structure of these power SOCs.

To fulfill demand from the area-sensitive products, eMemory is now providing the gen-2 NeoMTP with only two additional masks for memory cell implant adjustment. This MTP can further shrink 40% cell size, while keeping cell on/off ratio and erase performance. Furthermore, due to smaller cell size, reduced parasitic capacitances also relieve the peripheral memory driving circuit capability, thus leads to a smaller total IP size. It can be a good alternative MTP solution for those wishing for a compact IP area with better cost-efficiency....More