NeoEE

NeoEE is a single-poly embedded memory device offering the industry’s lowest implementation cost up to 500K program/erase cycles with low to medium densities (< 16K bits).

NeoEE carries out electronic program-/erase- operations for 16K bits (maximum) memory density and functions as a true rewritable memory technology, allowing up to 500K prgram/erase cycles with zero additional masking layers. A byte-write function is also incorporated in the NeoEE silicon IP to replace external EEPROM solutions and further reduce the package cost.

High Yield

Suitable for major foundries using CMOS technologies ranging from 0.35um~40nm

Fast Time to Market

No process tuning,easy porting to derivative processes

High Temperature Operation

Up to 150°C/10 Years Retention

Low Power

Low current consumption for programming

High Endurance

Robust F-N programming

Technical Principles

NeoEE is composed of capacitive-coupling MOS devices and selectors. The memory-cell uses FN-tunneling from various MOS devices to store and expel electric charge from the floating gate, thereby turning the floating-gate transistor on or off during read cycles.

NeoEE has a main memory array that enables program, erase, and write functions on a block-unit as a page or a word, allowing it to meet the needs of intensive and frequent write cycles on random addresses. NeoEE further incorporates a high-voltage generator and power switches in order to simplify the user interface and power supply maintenance. The additional logic controllers enable switching of power sources for a range of operating modes.

Use Cases & Functionality

NeoEE can be applied in various product fields, such as user-preference settings in IC cards, code storage in MCUs and RFICs, configuration settings in NFC controllers, fuse devices in memory redundancy designs, and parameter trimming for analog/RF/HV/BCD circuits. The core function of NeoEE technology enables frequent changes of system setting parameters, making NeoEE an ideal replacement for traditional external SPI flash and EEPROM chips.