MagnaChip EEPROM

The MagnaChip EEPROM series is a 2P4M non-volatile EEPROM IP block device that uses a MagnaChip SSTC EEPROM and is embedded into a Magnachip 0.18μm 1.8V/3.3V (5V) LP EEPROM process. The write scheme uses FN tunneling to achieve low-power operation. The silicon IP includes a built-in internal charge pump for read/write operations. The series was developed for system-on-a-chip (SoC) applications such as SIM cards, smart cards, RFIDs, medical devices and more. 

Low Power

VDD:1.62V~1.98V for read/write operation

Compact Macro Size

Small cell size

High Reliability

Reliable technology from FN tunneling unique cell

High Yield

High production record

Friendly Usage

Page write available

Technical Principles

The MagnaChip EEPROM cell consists of three transistors: one as a floating gate in the center and two as select gates at the side walls. The select gates are self-aligned to either side of the floating gate and act as control gates. Because the control gates surround the floating gate on all four sides, they exhibit strong capacitive coupling with the floating gate. Programming and erasure use Fowler–Nordheim (F-N) tunneling, which enables low-power programming/erasure and allows the cell to withstand up to half a million cycles. The MagnaChip EEPROM cell provides outstanding programming and erasure with superior reliability and data retention.

Use Cases & Functionality 

MagnaChip EEPROM can be applied in various product fields, such as code storage in micro-controllers, code storage in RFICs, and parameter trimming for analog/RF/HV (BCD) circuits. The core function of MagnaChip EEPROM technology enables frequent changing of system parameters, making MagnaChip EEPROM an ideal replacement for traditional external SPI flash and EEPROM chips. MagnaChip EEPROM provides a wide density range (16Kbits~512Kbits) for the following applications.

Please complete the following form then click 'send' to complete the download.
Note: all fields are required

Job title
Verification code