NeoMTP is a single-poly embedded memory technology offering high NVM memory density with 1K endurance at the lowest implementation cost to be found in the industry.
NeoMTP performs erase operations for max. 512K bits memory density and serves as a true rewritable memory technology up to 1K P/E cycling with zero additional masking layers. NeoMTP technology is equipped with an additional erase gate and is very similar to NeoBit for easy implementation.
NeoMTP is a NeoBit derivative which uses a 2T PMOS (1SG+1FG) for programming and a capacitive coupled Gox for erasing. This erasing gate is from FG extension at single poly process.
Like NeoBit, NeoMTP uses channel hot-hole to induce hot-electron injection into the floating gate (CHEI) for programming, thus turning on the channel of the p-type FG-MOSFET. NeoMTP uses Fowler-Nordheim (F-N) Tunneling to erase the bit cell. With the application of an erase gate voltage, electrons in the floating gate are pulled out the erase gate. When no electrons remain in the floating gate, the channel of the p-type FG-MOSFET is turned off. This easing operation is very low power consumption for using larger memory density.
NeoMTP is fully compatible with logic process, needing zero additional masks for 3.3V IO devices and 5V IO devices. Both types use a standard logic process without the need for any additional thermal budget. NeoMTP technology can deliver NVM block in system/in field programmability, maintaining high reliability, endurance and data retention over 10 years at 85° C 3.3V gate oxide) and over 10 years at 125° C (5V gate oxide) without any extra manufacturing costs.
NeoMTP is offered in three different applications. Existing silicon IPs with density up to 512k bits are available in 0.18um to 55nm CMOS process platforms, as listed below.
General: used for regular MCU code storage
High-temperature: operating temperature and data storage temperature up to 150° C for power-management and automotive applications
Green: a cost-effective solution for regular NeoMTP
|Process Nodes||0.18um~55nm 3.3V and 5V||0.13um/0.18um||0.18um/0.153um 5V|
|Retention||10 years @ 85° C/125° C||10 years @ 125° C/150° C||10 years @ 85° C|
|Program Power||External Vpp pad or internal charge pump||Internal charge pump||External Vpp pad or internal charge pump|
|Key Features||Fast read speeds (up to 20ns)||Read/Program/Erase up to 150°C
Meet automotive AEC-Q100
|Competitive production costs and wide operation voltage range|
NeoMTP has a broad range of applications, including touch panels, P-Gamma, MCUs etc. The core functionality of NeoMTP technology makes it ideal for setting system parameters for different chips in a single system, making NeoMTP an ideal replacement for traditional external SPI flash and EEPROM. In its current design, NeoMTP can go through up to 1000 P/E cycles, but it can also be specially designed to achieve 100 P/E cycle times to speed up product delivery time.
NeoMTP is being developed at 0.18um, 0.153um, 0.13um, 0.11um, 90nm, 80nm and 55nm technologies and designed in density up to 512k-bits. NeoMTP memory blocks can be set to x8 to x32 IO-configurations and read speed range can achieve from 20ns, 40ns to 200ns. Currently, NeoMTP silicon IP design has been verified at 0.153um 5V MR, 0.11um 1.2/3.3V logic, 0.11um 1.5/3.3V low leakage, 0.11um 1.5/5V HV, 80nm 1.2/6V HV, 55nm 1.2/6V HV, and 0.13um BCD processes. And, NeoMTP silicon IP design has passed qualification at 0.11um 1.2/3.3V logic and 80nm 1.2/6V HV processes.