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NeoEE

Introduction

NeoEE carries out electronic program-/erase- operations for 16k-bit (maximum) memory density and functions as a true rewritable memory technology, allowing up to 100K P/E cycling with zero additional masking layers. A byte-write function is also incorporated in the NeoEE silicon IP to replace external EEPROM solutions and further reduce the package cost.

Technical Principles

NeoEE is composed of capacitive-coupling MOS devices and selectors. The memory-cell uses FN-tunneling from various MOS devices to store and expel electric charge from the floating-gate, thereby turning the floating-gate transistor on or off during read cycles.

NeoEE comprises a main memory array that enables program, erase, and write functions on a block-unit as a page or a word, allowing it to meet the needs of intensive and frequent write cycles on random addresses. NeoEE further incorporates a high-voltage generator and power switches in order to simplify the user interface and maintenance of power supply. The additional logic controllers enable switching of power sources for a range of operating modes.

Advantages

In comparison to destructive solutions such as poly e-fuse or other oxide-rupture methods, NeoEE delivers an embedded EEPROM solution for CMOS logic and BCD-derivative processes, adding value to process platforms with rewritable memory to reinforce design functionality and testability. Fabless companies who adopt this solution will enjoy NeoEE’s in-system and in-field rewritability with economical power dissipation, multiple rewrite cycles, and high reliability without additional manufacturing costs. Furthermore, NeoEE requires no process or device tuning, so users will benefit from a fast time-to-market product cycle.

Specification

NeoEE is available in three types for a wide range of applications, as outlined below.

  • General: general-purpose specifications, suitable for a variety of consumer-grade products

  • High-temperature: operating temperature and data storage temperature up to 150 C for power-management and automotive applications

  • Green: a cost-effective alternative to external EEPROM with low-cost MCU products

NeoEE General High Temperature Green
Density 256bits~16Kbits 256bits~4Kbits 1Kbits~16Kbits
Process Nodes 0.18um~40nm 0.3um~0.11um 0.18um~0.153um
Retention 10 years at 85° C 10 years at 150° C 10 years at 85° C
Program Power internal charge pump internal charge pump internal charge pump
Key Features Compact IP size Read/Program/Erase up to 150° C Single voltage/Wide voltage range for external EEPROM replacement

Applications

NeoEE can be applied in various product fields, such as user preference settings in IC cards, code storage in MCUs and RFICs, configuration settings in NFC controllers, fuse devices in memory redundancy designs, and parameter trimming for analog/RF/HV/BCD circuits. The core function of NeoEE technology enables frequent changes of system setting parameters, making NeoEE an ideal replacement for traditional external SPI flash and EEPROM chips.

Availability

NeoEE is designed in density up to 16k-bits and available at 10 foundries, ranging from 0.3um BCD to 0.11um logic technologies. In addition, 65nm LP technologies are currently in development. NeoEE memory blocks can be set to x1, x8 or x16 IO-configurations.