NeoBit uses logic-based architecture for an embedded non-volatile memory (eNVM) design that eliminates the need for additional masking layers or extra process steps typically associated with eNVM. NeoBit embeds seamlessly into a variety of CMOS processes, including logic, mixed-mode, bipolar-CMOS-DMOS (BCD), analog, radio-frequency (RF), and high-voltage (HV).

Technical Principles

NeoBit is composed of two p-MOSFET connected in series, one as a floating gate transistor and the other as a select transistor.

NeoBit uses a channel hot hole to induce hot electron injection (CHEI) into the floating gate to program the bit cell. The lateral high-electric field accelerates holes and leads on electron-hole pair generation. The electrons that form the electron-hole pairs are injected into the floating gate via a coupling effect between the floating gate and the drain. Electrons stored in the floating gate turn on the channel of the p-type FG-MOSFET.


NeoBit’s process simplicity makes the technology extremely robust. The principal benefits of NeoBit design are high fabrication yield and fast time-to-market. The efficient programming interface also brings the benefit of short turnaround times with fast and reliable erasure through UV exposure. Additional advantages of NeoBit include low manufacturing and development costs and the industry’s widest process scalability.


Six types of NeoBit are available for a variety of applications. Existing silicon IPs with densities up to 16M bits are available in 0.5um to 55nm CMOS process platforms.

  • General: used for general MCU code storage.

  • Trimming: used for LCD drivers, PMIC trimming, and parameter setting.

  • Ultra-Low Power (ULP): for IoT applications.

  • Automotive: designed for automotive-grade applications.

  • Pseudo MTP (PMTP): similar to trimming NeoBit with additional program/erase capability (< 10 cycles.)

  • Green: cost-effective solution for regular NeoBit.

NeoBit General Trimming ULP
Density 4K~512Kbits 8~32Kbits 8~4Kbits
Process Nodes 0.5um~55nm 0.5um~55nm 0.35um~0.18um
Retention >10 years @ 85°C >10 years @ 150°C
(depends on process)
>10 years @ 85°C
Program Power External Vpp pad or internal charge pump External Vpp pad or internal charge pump External Vpp pad or internal charge pump
Key Features Faster read speed
(up to 25ns)
High reliability
(2 Cells/Bit)
Ultra-low power consumption and low operation voltage
NeoBit Automotive PMTP Green
Density 256~16Kbits 8~4Kbits 512~16Mbits
Process Nodes 0.25um~0.13um 0.35um~90nm 0.18um/0.153um
Retention >10 years @ 150°C
(depends on process)
>10 years @ 85°C >10 years @ 85°C
Program Power External Vpp pad or internal charge pump External Vpp pad or internal charge pump External Vpp pad or internal charge pump
Key Features Meets AEC-Q100 criteria Additional program/erase capability (< 10 cycles) Compact IP area and wide operation voltage range


NeoBit has a broad range of applications: code storage in microcontrollers (MCUs), parameter setting in NB camera controllers, encryption in set-top boxes (STBs), fuse devices in memory redundancy designs, function selection in SoC chips, and trimming for analog and RF circuits. NeoBit is the ideal replacement for traditional ROM and EPROM system designs.


Silicon-proven at 17 major foundries in over 315 qualified process platforms.