For some NVM applications, customers need both program NVM and data memory. OTP may be sufficient for program memory, but MTP or EEPROM is needed for data memory. The NeoBit + NeoMTP Hybrid silicon IP satisfies both these requirements.

Technical Principles

Customers define hybrid silicon IP specifications according to their requirements. NeoBit and NeoMTP share peripheral circuits in order to minimize the size of the silicon IP.


Macro size is reduced because NeoBit and NeoMTP share certain circuits. In addition, customers can use one simple IO and command to access the hybrid NVM silicon IP.


Hybrid NeoBit + NeoMTP or NeoBit + NeoEE
Density Total density ≥ 8k8, NeoMTP or NeoEE density defined by customer
Process Nodes 0.11um 1.2V/3.3V logic process
Retention 10 years @ 85° C
Program Power External Vpp pad or internal charge pump
Key Features Competitive production costs


Our hybrid silicon IPs are the best solution for MCU-like chips with both code storage and data storage requirements.


The first hybrid silicon IP has been verified on a 0.11um 1.2/3.3V logic process and 0.18um Green process.