Products

MagnaChip EEPROM

Introduction

MagnaChip EEPROM series is a 2P4M non-volatile EEPROM IP block device which uses a MagnaChip SSTC EEPROM and is embedded into a Magnachip 0.18μm 1.8V/3.3V (5V) LP EEPROM process. The write scheme uses FN tunneling to achieve low-power operation. The silicon IP is implemented with a built-in internal charge pump for read/write operations. The series was developed for system-on-a-chip (SoC) applications such as SIM cards, smart cards, RFIDs, medicals etc.

Technical Principles

MagnaChip EEPROM cell consists of three transistors: one as a floating-gate in the centre and two as select gates at the side walls. The select gates are self-aligned to either side of the floating gate and act as control gates. Because the control gates surround the floating gate on all four sides, they exhibit strong capacitive coupling with the floating gate. Programming and erasure use Fowler–Nordheim (F-N) tunneling, which enables low-power programming/erasure and allows the cell to withstand up to half a million cycles. The MagnaChip EEPROM cell provides outstanding programming and erasure with superior reliability and data retention.

Specification

MagnaChip EEPROM is offered for a wide range of applications. Existing silicon IPs with density up to 512k bits are available on MagnaChip 0.18um CMOS process platforms.

MagnaChip EEPROM General
Density 4k8~64k8
Process Nodes 0.18 um
Retention 10 years @ 85° C
Program Power Internal charge pump
Key Features Compact IP size Single Power

Applications

MagnaChip EEPROM can be applied in various product fields, such as code storage in micro-controllers, code storage in RFICs, and parameter trimming for analog/RF/HV (BCD) circuits. The core function of MagnaChip EEPROM technology enables frequent changing of system parameters, making MagnaChip EEPROM an ideal replacement for traditional external SPI flash and EEPROM chips. MagnaChip EEPROM provides a wide density range (16Kbits~512Kbits) for these kinds of applications.

Availability

MagnaChip EEPROM is currently being developed in MagnaChip 0.18um technologies and designed in density up to 64k8-bits. MagnaChip EEPROM memory blocks can be set to either x8 or x16 IO-configurations.