Applications

Trimming

What is Trimming?

The circuit design of analog ICs and SoCs includes specifications that define the parameters for the input and output of analog signals; however, small physical shifts in manufacturing flow, such as foundry process shift or stress resulting from the packing process, can cause the analog signal to shift from its target specification. This deviation must be corrected or compensated for in high-precision applications. For example, screen brightness must be consistent for any given model of mobile phone. Trimming helps compensate for shifts in screen brightness, which result from the production process, and ensures that all phones coming off the final production line have similar levels of screen brightness.

eMemory’s embedded NVM IP provides a small memory array for storing trimming information within the IC (Fig. 1). Information recorded within the NVM IP can be used to precisely adjust the input or output signal of the analog device (Fig. 2). This function can be executed at the CP or FT level.

Applications

Product Target Proposed Usage eMemory NVM Silicon IP
TFT LCD Driver Driving current Reference voltage Measuring and setting in CP/FT/System stage Density: 8-2K bits
P/E Cycle: 1~10
IP: NeoBit, NeoFuse
LED Management IC Driving current, Voltage setting, ADC Measuring and setting in CP/FT/System stage Density: 8-2K bits
P/E Cycle: 1~10
IP: NeoBit
LCD TV Controller ADC, DAC, PLL, Regulator Measuring and setting in CP/FT/System stage Density: 8~2K bits
P/E Cycle: 1~10
IP: NeoBit, NeoFuse
Power Management IC DC/DC, Regulator Measuring and setting in CP/FT/System stage Density: 8~2K bits
P/E Cycle: 1~1K
IP: NeoBit, NeoFuse, NeoEE
STB Controller DAC, PLL, Regulator Measuring and setting in CP/FT/System stage Density: 8~2K bits
P/E Cycle: 1~10
IP: NeoBit, NeoFuse
Image Capture Controller ADC, DAC, PLL, Regulator, CCD/CMOS Measuring and setting in CP/FT/System stage Density: 8~2K bits
P/E Cycle: 1~1K
IP: NeoBit, NeoFuse

Benefits of Trimming with eMemory’s Logic NVM Silicon IPs

Conventional metal or poly fuse circuits can provide fine tuning of these sensitive analog signals (Fig. 3), but a large current must be supplied from the external environment to internal adjusted points of the IC in order to burn out the metal or poly line. This large current flow must be set up very carefully, or it will cause damage to other circuits in the chip. In addition, circuits near the metal or poly fuse may be contaminated by residue from the blowout, and the final yield may decrease. Using eMemory’s Logic NVM for trimming can eliminate these problems.

eMemory Logic NVM Silicon IP offers the most flexibility for fine tuning sensitive signals. Other benefits include:

  • Testable at CP stage, thus avoiding yield loss at FT/Module/System stages.

  • Trimming available at different stages, including CP, FT, Module, and System stages.

  • Smallest silicon IP size in mainstream processing of consumer electronic ICs.

  • Electronic program avoids residue contamination of poly/metal fuse.

  • Silicon-proven at 20 major foundries and available in over 250 qualified processes.

  • Support for logic, mixed-signal, RF, high-voltage, BCD, SiGe, automotive, and low-power processes.