Microcontroller units (MCUs) have found a wide range of applications in consumer electronics, industrial control, automotive electronics, and household appliances. Conventionally, an MCU chip requires dedicated memory, such as ROM, for three purposes: first, ROM can be used to store software programs, with instructions written in one or more ROM words; second, ROM functions as a constant data storage unit in the MCU system; and third, ROM implements a combinational logic circuit. However, mask maintenance and programmability are major concerns in traditional mask ROM solutions. To resolve these issues, eMemory is offering NeoBit, NeoFuse, NeoFlash, and NeoMTP—a range of innovative and competitive memory silicon IP solutions. In addition, eMemory provides NeoBit customers with a service called NeoROM: an OTP-to-ROM conversion program that enables customers to reduce back-end testing overheads for fixed-code products without modifying the whole circuit layout, but by implementing only a single layer change instead.

NVM Silicon IPs for ROM Replacement

Within the eMemory silicon IP family, NeoBit, NeoFuse, NeoFlash, and NeoMTP, are a series of products designed specifically as ROM replacements. Available in densities ranging from 2K to 8M bits, these products allow customers to optimize code storage efficiency with maximum flexibility. With their powerful advantages over traditional ROM, such as programmability and testability, NeoBit, NeoFuse, NeoFlash, and NeoMTP spare users from version-to-version mask maintenance and inventory concerns. In addition, NeoBit and NeoFuse have a logic-based architecture that requires no additional masking layers or extra processes, thus adding the extra benefit of short time-to-market. Currently, NeoBit is available in a variety of technologies and configurations through multiple foundries, and NeoFuse is also being developed at multiple foundries. NeoFlash only needs 2–3 extra masks in order to provide embedded flash silicon IP for ROM replacement. NeoMTP is a NeoBit cell derivative, serving under 512K bits with an endurance of 1K–10K cycles, which is a good balance between macro size and masking layers in addition to the use of NeoFlash for low density ROM replacement.

MCU Block Diagram