eMemory provides full functional hard macro Neobit Macro which is totally compatible with logic or logic-derivative processes. Due to its simplicity in device structure and processes, Neobit can be easily implemented in different generations of logic technologies and ported to logic derivative technologies, such as mixed-mode, RF, analog, high voltage, embedded memories and etc., without changing any process or its device simulation model. It assists customers in realizing SOC(system-on-chip) applications in a most convenient and competitive way. The cost-effective process can be adopted in various products, such as MCU, DSP, cellular communications, smart card, DVD, voice and speech ICs.

Neobit Macro is currently available in technologies from 0.5 um, 0.35um , 0.25um to 0.18um . The most competitive and popular density size varies from 512K bits to several K bits. In addition, several different IO configurations are available: x8 bits, x14 bits, or x16 bits. Customers can easily plug it in to replace mask ROM or EPROM in their original product design.

Due to the reliable operation scheme and robust macro design, the average yield of Neobit Macro can simply be treated as ASIC logic's performance. In 0.35um for instance, yield of 512K Neobit Macro can reach 98% and above. Customers will not have to worry about product yield reduction after Neobit Macro adoption.

Advantage

In comparison with mask ROM and EPROM, Neobit Macro has several advantages as listed below:

Technology Neobit Macro Mask ROM EPROM Compatibility to logic process Yes Yes No SPICE model aligned to logic Yes Yes No Additional masks to logic process 0 +1 ROM mask +3 masks or more Wafer processing cost Low Low Medium Technology development time 3~6 month 3~6 month 1~2 years Technology scalability Easy Easy Difficult In-system programming Yes No Yes Erasability Yes, by UV No Yes, by UV IP macro size Medium Small Large Time to market Fast Slow Fast

Application Suggestions

● To be ROM replacement 　• great flexibility by electrical programming which allows code implementation after wafer fab out 　• no inventory of wafer storage in-line 　• fast time to market 　• no additional coding mask and maintenance issue 　• high code security ● To be EPROM replacement 　• Neobit Macro uses pure logic process which has fewer masking layers and lower wafer price 　• Neobit Macro realizes SOC applications since logic device model does not change for design-in 　• Neobit Macro is available in wide range technology generations and can provide higher scaling-down opportunity than EPROM

Product Feature:

● 0.35um Neobit Macro 　 • Operation voltage: 2.7V to 4.0V 　 • Byte program time: 100us(max) with external VPP pad (internal pumping circuit is optional) 　 • Read speed: <40ns for asynchronous design 　 • Read operation current: Icc~3mA@25MHz(typ) 　 • Standby current: <1uA 　 • Temperature range –40°C ~ 85°C 　 • Data retention: 10 years(min) ● 0.25um Neobit Macro 　 • Operation voltage: 2.25V to 2.75V 　 • Byte program time: 100us(max) with external VPP pad (internal pumping circuit is optional) 　 • Read speed: <25ns for synchronous design 　 • Read operation current: Icc~7mA@40MHz(typ) 　 • Standby current: <1uA 　 • Temperature range –40°C ~ 85°C 　 • Data retention: 10 years(min) ● 0.18um Neobit Macro 　 • Operation voltage: 1.6V to 1.8V 　 • Byte program time: 100us(max) with external VPP pad (internal pumping circuit is optional) 　 • Read speed: <25ns for synchronous design 　 • Read operation current: Icc~5mA@40MHz(typ) 　 • Read Standby current: <1uA 　 • Temperature range –40°C ~ 85°C 　 • Data retention: 10 years(min)